Chemical mechanical planarization (CMP)—also referred to as chemical mechanical polishing—is a common technique used in semiconductor processing to remove topography from thin films or other surfaces. CMP processes involve applying a chemical solution, such as a slurry containing an abrasive material, between a surface of a semiconductor workpiece and a rotating pad. Pressure is applied to the polishing pad such that the chemical solution, abrasive materials in the slurry, and/or the pad remove material from the surface of the semiconductor workpiece until a desired amount of material has been removed from the surface. Additionally, the process is often continued until the surface is substantially planar.
One challenge of CMP processes is the difficulty to achieve the requisite planarity. For example, when the surface includes relatively large “open” areas (e.g., areas having a low density, or no circuit elements, such as wires, interconnects, etc.), CMP can cause dishing of the thin film which introduces undesired topography. Previous attempts to address this problem have included adding fill structures in the open regions. However, adding fill material in such regions is impractical in certain processes, such as more recent vertical integration schemes that require regions which cannot accept a fill material. To address this problem in vertical integration schemes, carbon has been implanted into an SiOx film to change the CMP material removal rate in select areas. The introduction of carbon into dielectric materials, however, can interfere with subsequent processing steps. For example, implanting a dielectric material with carbon may make it more difficult to subsequently etch vias or conduct post-clean steps. There also needs to be the ability to choose implant species which can accommodate different integration schemes. Accordingly, there remains a need to develop practical methods to improve CMP planarity control in open areas of a wafer without interfering with subsequent processing steps.